Semiconductor die (e.g. light emitting diodes (LEDs) and high power transistors) have flat mounting surfaces and are attached to flat package surfaces using various organic (epoxy-like) or inorganic (solder) attachment methods for packaging the bare semiconductor element (die). This process is known generically as a die attach (D/A) process and the adhesives or solders are known as D/A materials. In addition to holding the die inside the package for subsequent assembly operations like wirebonding and overmolding, this combination of die and package surfaces and D/A materials need to meet several other requirements:                Accommodate any expansion/contraction of the chip, the package and the die attach material occurring during thermal cycling, which is due to coefficient of thermal expansion (CTE) mismatches between the semiconductor die and the packaging materials.        Provide high thermal conductivity for conducting heat from the semiconductor die through the package and to the package external surfaces efficiently.        Be nominally free of voids between the semiconductor die and the mating package surface, for both improved strength and better thermal management.        Be amenable to high speed assembly processes to ensure low cost of manufacturing.        
Ordinarily, the package and die surfaces are clean and flat. But both CTE management and voiding becomes problematic for larger die, and failure can become more of a problem. Voiding can be managed by performing curing or soldering operations in a vacuum environment, but this can be slow and adds expense to the packaging operation.
Consequently, a fundamental challenge for high power semiconductor device manufacturing and reliable operation involves the creation of a mechanically-stable and thermally-conductive interface between the semiconductor die (where heat is generated) and the package that houses the die and is typically attached to circuit boards to create modern electronic and electro-optical systems. A generic structure that illustrates the challenges encountered in the prior art is shown in FIG. 1, where the D/A material is shown with voids (air gaps) 4 that typically occur during high volume manufacturing operations. Specifically, FIG. 1 illustrates the semiconductor die 1, the D/A material 2, and the package 3 (typically attached at a metal part thereof to the D/A material 2). The direction of heat flow is shown by the downward-pointing arrows. Voiding is shown as gaps 4 in the D/A material 2. These voids 4 can impact both the mechanical stability and thermal performance of the finished device, compromising reliability in operation. There are two related problems that need to be addressed to improve the overall performance of the assembly shown in FIG. 1. The first is to improve the thermal performance. The second is to improve the mechanical performance.
As to thermal performance, semiconductor devices degrade more rapidly at high temperatures than at lower temperatures. The heat generated in the semiconductor die 1 during operation typically needs to be conducted to the environment through the package 3. The efficiency of the cooling process depends on the thermal conductivity of all the materials shown in FIG. 1, as well as the number of interfaces through which thermal energy needs to be transported. The types of interfaces shown in FIG. 1 include:                Die 1 to air interface (voids 4)        Air to package 3 interface (voids 4)        Air to D/A material 2 interface (voids 4)        Die 1 to D/A material 2 interface        D/A material 2 interface to package 3        
Studies have shown that even when high thermal conductivity materials (die 1, D/A material 2, package 3 materials) are used, transporting thermal energy from one type of material to another, or through air pockets, is a major problem. Generally speaking, this thermal interface resistance is a fundamental property that depends on the materials involved and how heat is transferred at the atomic or molecular level between different types of materials, characterized, for example, by different types of atomic and molecular bonds. Typically, the thermal transport can be characterized in a simplified impedance diagram such as is shown in FIG. 2, which shows a representative, non-limiting example for a complex assembly of die, D/A material, and package. The chip shown here is thermally representative of a typical blue LED where the junction of the LED is in a very thin semiconductor layer on top of the sapphire substrate shown. Of particular interest here is the fact that the thermal path can be described and modelled as a series of thermal “resistors” that impede the transport of heat. FIG. 2 is representative of several of the interfaces in the structure, and the presence of voids 4 can be seen. Note that the specific thermal impedances depend on the specific thicknesses of the layers, which are not shown to scale.
The state of the art involves minimizing the number of interfaces, maximizing the bulk thermal conductivity of all of the materials involved and minimizing the occurrence of voiding. Reducing the thermal interface impedance has only been approached in state-of-the-art packaging to date, by reducing the overall number of interfaces. There appears to have been little if any attention given to changing the fundamental structure of the interfaces involved.
As to mechanical performance, modern electronic devices need to operate over a wide range of temperatures. Because most materials used in semiconductor packaging expand different amounts with increasing temperature, mechanical strain can be introduced during thermal cycling of a typical semiconductor part. Shown in FIG. 3 is an image of a failed prior art solder joint in a semiconductor package following thermal cycling reliability testing. The mechanical stability of this part of the package depends on the thermal expansion coefficients of all the materials involved, their elasticity (ability to stretch under strain), the physical dimensions of the interface and the degree of adhesion between the thermal D/A material 2 used and the package 3 and semiconductor die 1 surfaces. Ordinarily, this is managed through a careful cleaning and polishing of interfaces to prevent voiding 4, and through controlling the thickness (usually referred to as a bond line thickness, or BLT) of the D/A material 2 to help distribute strain over a larger distance. Of course, thicker die attach adhesive thicknesses (greater BLT) are better for mechanical reliability, but greater thicknesses also increase thermal resistance. Ideally, one would want to keep the thickness of the thermal interface adhesive material as thin as possible for better thermal performance while also providing high mechanical strength and reliability.
A summary of many of the areas being pursued in the prior art to improve the thermal performance and mechanical stability of modern semiconductor packages is shown in FIG. 4. A wide variety of sophisticated technologies are being employed, but the key interface technologies involve filling in the roughness at the die 1 and package 3 interfaces with the thermal interface adhesive to manage micro-voiding (the nano-sponge materials are shown as roughness fillers). Again, little if any attention has been given to changing the fundamental structure of the interfaces involved.